02 nov
|
Allegro MicroSystems
|
Tandil
02 nov
Allegro MicroSystems
Tandil
Allegro MicroSystems is seeking a Senior IP Engineer to design NVM/memory IP and support the release of Foundry mask requirements for a integral design community. You will work in a Design Enablement group, coordinating with device development and EDA teams, and contribute to the BCD technology roadmap.
The role requires a BSEE with 2+ years of memory/memory IP experience, proficiency with Cadence tool flows, and knowledge of Verilog-based HDL.
📌 Memory IP Engineer (Tandil)
🏢 Allegro MicroSystems
📍 Tandil