Celero Communications, a fast-growing semiconductor startup, is seeking a High-Speed Analog Layout Design Engineer to drive layout development of analog/mixed-signal IP blocks such as ADCs, DACs, PLLs for our optical communication systems.
You will mentor junior layout engineers across time zones, work with circuit designers and CAD/PDK teams, and ensure first-pass silicon success through thorough LVS/DRC checks and robust floorplanning.
📌 Lead High-Speed Analog Layout Engineer — Mentor (Córdoba)
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