Mixed Signal Design Verification Engineer (Buenos Aires)

Mixed Signal Design Verification Engineer (Buenos Aires)

15 oct
|
Allegro MicroSystems
|
Buenos Aires

15 oct

Allegro MicroSystems

Buenos Aires

The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and the communities we serve.
The Opportunity
Allegro MicroSystems is seeking an enthusiastic and motivated Mixed-Signal Design Verification (MSDV) Engineer to join our development team. In this role, you will work under the guidance of senior technical leads to develop and execute top-level mixed-signal verification testbenches for our market-leading automotive and industrial integrated circuits. You will act as a key interface between transistor-level analog building blocks and digital control systems, running functional simulations across power sequencing, register configurations, and system-level testcases to ensure first-pass silicon success.
What You Will Do




Run and debug top-level AMS simulations using Cadence AMS Designer and Virtuoso to verify chip-level interactions between analog front-ends and digital logic. Assist in writing and maintaining behavioral models and testbenches using Verilog, SystemVerilog, and Verilog-AMS/Real-Number Modeling (RNM/wreal). Verify power-up/power-down sequences, brown-out events, and reset circuitry (POR, POK, UVLO) across voltage and temperature corners to ensure proper start-up behavior. Validate register maps, EEPROM configuration loads, read/write protocols, and trim test modes against design specifications. Log and track verification bugs using GitLab issue tracking, applying standard workflow states (Analysis Pending, Verified) to support tapeout readiness. Partner with Analog Design, Digital Design, and Systems Engineering to review coverage metrics in Jama Connect and support testcase closure. What You Will Bring
Bachelor’s or Master’s degree in Electrical Engineering, Com

📌 Mixed Signal Design Verification Engineer (Buenos Aires)
🏢 Allegro MicroSystems
📍 Buenos Aires

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