At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This is an opportunity to join a dynamic and growing team of engineers developing extremely high-speed wireline communications transceivers in CMOS silicon.

This job opening is for Numerical Modeling & Architecture, helping guide the selection and specification of transceiver components using mathematical and computer modelling techniques.

The candidate will collaborate with analog designers, digital designers, applications engineers, and marketing specialists to help guide tradeoffs among conflicting design goals, and as such will be responsible for the performance of the end-to-end system.

This will also require involvement in lab characterization and analysis of finally realized designs. The position is full-time in our San Jose office.

Position Requirements:

The ideal candidate will have several of the following:





- The ability to think through engineering systems end-to-end and identify bottlenecks and weak points.
- Strong mathematical skills, in particular relating to linear systems (Fourier analysis, filter theory, etc.)
- Deep knowledge of communication systems fundamentals
- Strong coding skills for simulation and modelling, as well as data analysis
- Good experimental skills.
- Good knowledge of signal processing (DSP) algorithms and architecture.
- Good working knowledge of physics of signal propagation
- Good working knowledge of basic circuits
- Demonstrated capacity to self-educate themselves to pick up new fields of expertise

The adecuado candidate will likely have a PhD in the mathematical or physical sciences.

We’re doing work that matters. Help us solve what others can’t.

We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.

📌 Principal Design Engineer (San Nicolás)
🏢 Cadence Design Systems
📍 San Nicolás