Celero Communications, Inc. is seeking a High-Speed Analog Layout Design Engineer to drive the layout of complex analog/mixed-signal IP blocks for advanced optical communication systems.
You will lead layout development of ADCs, DACs, PLLs and related circuits, interfacing with circuit designers and CAD/PDK teams to ensure first-pass silicon success. You will mentor junior engineers, perform signoff checks, and contribute to chip-level planning and tool automation.
📌 Lead High-Speed Analog Layout Engineer for IP Blocks (Córdoba)
🏢 Celero Communications
📍 Córdoba
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