Job Oportunity at Emtech

Semi-senior RTL Design Engineer

As a member of our dynamic group, you will have the opportunity to work as a Semi-Senior RTL Design Engineer in high-tech FPGA and ASIC projects.

Responsibilities

Design and implement complex RTL modules for various technologies.

Perform RTL code reviews to ensure compliance with code guidelines.

Develop detailed test plans to validate functionality and performance.

Work actively to optimize design for power, area and timing.

Mentor and guide junior engineers in the team.

Create and maintain documentation for new designs.

Key Qualifications

Strong understanding of advanced digital design concepts, such as pipelining, clock domain crossing and state machines design.

Advanced knowledge of synthesizable VHDL, Verilog or SystemVerilog.

Experience with high-speed interfaces, memory controllers and DSP blocks.





Experience with in-chip buses such as AMBA AXI and Wishbone.

Background in verification methodologies such as UVM is a plus.

Proficiency in scripting languages such as Python, TCL, and Bash.

Experience with version control systems such as Git.

Excellent communication skills in English for expressing complex ideas and taking part in design discussions.

Ability to work independently and collaboratively in a team environment.

Full remote

‍Education & Experience

MSEE degree with +2 years of industry experience

BSEE degree with +3 years of industry experience

Experience with specifying or implementing digital signal processing schemes is a plus

Contact: [email protected]

📌 Semi-Senior Design Verification Engineer (SystemVerilog UVM) (Argentina)
🏢 EmTech
📍 Argentina