The Allegro team is united by a clear purpose—advancing technologies that make
the world safer, more efficient, and more sustainable. With over 30 years of
experience in semiconductor innovation, we bring that purpose to life across
every part of the business—from breakthrough product development and customer
success to how we show up for each other and the communities we serve.
About the Department
The Technology Development group is an integral organization of Allegro that
includes Device Development, Foundry Operations, Modeling, ESD/EMC, and Design
Enablement teams. The group facilitates all semiconductor devices and design
automation research and development programs from concept through maturity. We
ensure that the technology roadmap is aligned with the product roadmap and work
across organizations. We manage partnerships with external foundries and
suppliers to deliver cutting-edge semiconductor devices and design automation
tools to support the product roadmap.
The Opportunity
The Device Layout and Mask Tooling Engineer will report to the Principal Design
Enablement Engineer and will play a critical role in supporting the Design
Enablement team. This role will perform semiconductor device layouts in EDA
software environment for semiconductor technology development and device
modeling. In addition, this role will support the release of Foundry mask
manufacturing requirements for a global design community. Candidate is
responsible for developing and supporting internal/external mask tape out
systems, generating and verifying GDS mask data, and MPW/Shuttle releases. This
work directly impacts the development of our BCD technology and the success of
our general design community.
What You Will Do
* Generate semiconductor component layouts in Cadence to support semiconductor
technology development, process technology transfers, and device modeling.
* Primary interface and support of product design MASK/GDS releases to Foundry.