We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits.
You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role idóneo for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.

Key Responsibilities Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry,



and reliability Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.) Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus) Required Qualifications Minimum 10+ years of hands-on analog/mixed-signal layout design experience and in advanced CMOS/FinFET technologies Proven track record of top-level integration IP layout macros and prep

📌 Senior/Principal High-Speed Analog Layout Design Engineer (Córdoba)
🏢 Celero Communications
📍 Córdoba