Candidate must have a Bachelor’s degree in either Electrical Engineering or Computer Engineering.

Experience with one or more ASIC verification languages and associated methods for creating self-checking testbenches for efficient ASIC verification: System-Verilog/Vera; eLanguage; System-C; C++ Experience with the following verification techniques: Testbench Automation; Constrained-Random Verification; Assertion-Based Verification; Functional Coverage-Driven Verification; Formal Verification (Static and Dynamic); Transaction-Level Modeling; A positive,



can-do attitude is required Good English communication skills a must RTL coding and synthesis using Verilog or VHDL languages Equivalence checking Good English communication skills a must Experience and knowledge of Static Timing Concepts and practical experience using industry standard tools – Synopsys Primetime preferred.

Experience and knowledge of Design for Testability and ATPG concepts and practical experience using industry standard tools (Synopsys Tetramax/DFT Compiler or Mentor Fastscan) Experience with Cadence Verilog NC/XL, Mentor Model

Sim or Synopsys VCS Simulators Experience and practical application of general IC design concepts and considerations (e.g. SSO analysis, Power analysis, cross coupling effects, timing closure, etc.)

📌 ASIC Verification Engineer - RTL & Formal Verification (Argentina)
🏢 Trustic
📍 Argentina