Satellite FPGA Engineer: IP Core Design & Verification (Buenos Aires)

Satellite FPGA Engineer: IP Core Design & Verification (Buenos Aires)

01 ago
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Jobtailor
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Buenos Aires

01 ago

Jobtailor

Buenos Aires

Descripción de la vacante Salario: $ 900.000 – $ 1.300.000 Jobtailor is seeking an embedded hardware engineer to design, verify, and document IP Cores for satellite systems. The role involves reviewing and testing IP Cores, integrating hardware and software in plant facilities, and creating comprehensive design documentation.

The candidate will interact with software and hardware designers and contribute to validation procedures, staying current with technology trends to enhance satellite designs and team guidelines.

📌 Satellite FPGA Engineer: IP Core Design & Verification (Buenos Aires)
🏢 Jobtailor
📍 Buenos Aires

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