Memory Design Engineer — Shape Next‑Gen Silicon IP (Buenos Aires)

Memory Design Engineer — Shape Next‑Gen Silicon IP (Buenos Aires)

23 may
|
Allegro MicroSystems
|
Buenos Aires

23 may

Allegro MicroSystems

Buenos Aires

Allegro MicroSystems, LLC is seeking a Memory Design Engineer in Buenos Aires.

The candidate will design and verify standard IP memories, including SRAM, ROM, and EEPROM, impacting BCD technology development.

The role requires a BSEE and 2 years of experience in memory design and EDA tools.

The successful candidate will collaborate with integral teams, documenting and publishing IP specifications.

Join Allegro to innovate and create real impact in semiconductor development.

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📌 Memory Design Engineer — Shape Next‑Gen Silicon IP (Buenos Aires)
🏢 Allegro MicroSystems
📍 Buenos Aires

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